This invention relates to gate-source structures for static induction transistors and, in particular, to a surface gate structure which improves device performance and which requires relatively simple fabrication techniques.
The static induction transistor is a field effect semiconductor device capable of operation at relatively high frequency and power. The transistors are characterized by a short, high resistivity semiconductor channel which may be controllably depleted of carriers. The current-voltage characteristics of the static induction transistor are generally similar to those of a vacuum tube triode. The devices are described by Nishizawa et al in U.S. Pat. No. 3,828,230 issued Aug. 6, 1974.
The static induction transistor generally uses vertical geometry with source and drain electrodes placed on opposite sides of a thin, high resistivity layer of one conductivity type. Gate regions of opposite conductivity type are positioned in the high resistivity layer on opposite sides of the source. During operation a reverse bias is applied between the gate region and the remainder of the high resistivity layer causing a depletion region to extend into the channel below the source. As the magnitude of the reverse bias is varied, the source-drain current and voltage derived from an attached energy source will also vary.
The design and fabrication of the gate-source structure is difficult. In order to operate at frequencies near or above 1 GHz, such devices must be built under extremely precise dimensional control. Involved dimensions are in the micrometer range, requiring photolithographic alignments with submicrometer precision.
The requirement for precise dimensional control makes the processing of high-frequency semiconductor devices costly and difficult. It is desirable to eliminate fabrication steps requiring precise mask registration and to, where possible, use procedures in which elements of the transistor are self-aligned.